This application incorporates Taiwanese application Serial No. 89125656, Filed Dec, 01, 2000.
1. Field of the Invention
The invention relates in general to a chip package, and more particularly to a super low profile package with high efficiency of heat dissipation.
2. Description of the Related Art
Recently, a trend of increasing the number of input/output (I/O) lead has developed so that the size of a chip package is increased after mounting die in the packaging process; therefore, it is important to minimize the size of the package and the thickness of the plastic mold in order to reduce the overall size of the chip package.
A method for reducing the package size of a chip package invented by Barry M. Miles and Glenn E. Gold is disclosed in U.S. Pat. No. 5,696,666. Referring to FIG. 1A, which depicts an upward view of the conventional chip package 100, the chip package 100 includes the substrate 102 and the die 104. The die 104 is seated in the cavity 106 that is located in the center of the substrate 102, and a number of the solder balls 109 are seated on the bottom side 110 of the substrate 102.
FIG. 1B depicts a cross-sectional view of the chip package along the sectional line 1Bxe2x80x941B in FIG. 1A. In FIG. 1B, the die 104 is wire-bonded to the substrate 102 via the wires 112 and 114, and the plastic mold 116 is applied on the topside 118 of the substrate 102; hence, the die 104 and the wires 112, 114 are encapsulated in the plastic mold 116. The topside 118 of the substrate 102 is opposite the bottom side 110 of the substrate 102. H1 and H4 represent the thickness of the substrate 102 and the chip package 100, respectively. H2 represents the distance from the topside 117 of the plastic mold 116 to the topside 118 of the substrate 102, the minimal value of which is approximately 0.2 mm. H3 represents the height of the solder balls 109, the minimal value of which is approximately 0.3 mm. The thickness of the die 104 is equal to, or thinner than, the substrate 102. H5 represents the distance from the highest point of the wire 119a/19b to the topside 118 of the substrate 102, and the minimal value is approximately 0.15 mm that is smaller than H2. Therefore, the overall thickness H4 of the conventional chip package is equal to the sum of H1, H2 and H3, wherein the minimal overall thickness H4 is approximately 0.7 mm.
FIGS. 2A, 2B, 2C and 2D depict the process of making the conventional chip package illustrated in FIGS. 1A and 1B. Referring to FIG. 2A, the cavity 106 is formed in the substrate 102a, and the tape then is adhered on the bottom side 110 of the substrate 102a to seal the opening 133 below the cavity 106.
Referring to FIG. 2B, the die 104 is seated in the cavity 106 and held with the tape 130, wherein the front surface 115 of the die 104 is toward to the same direction as the topside 118 of the substrate 102a. The die 104 is then wire-bonded using conventional techniques, and the die 104 and the substrate 102a is electrically connected by the wires 112, 114 on the front side 115 of the die 104. Encapsulation subsequently proceeds; the die 104 is filled with the plastic mold 116 to a predetermined level. The plastic mold 116 that encapsulates the die 104, wire 112 and wire 114 provides strong mechanical support for the die 104 in order to stabilize the die 104 in the substrate 102a. 
After the die 104 is fixed to the substrate 102a by the plastic mold 116, the tape 130 is not needed; therefore, de-taping is then proceeding as shown in FIG. 2C, resulting in the bottom side 132 of the die 104 is exposed to the atmosphere.
Subsequently, solder ball placement proceeds, wherein the numerous solder balls 109 are seated on the bottom side 110 of the substrate 102a as shown in FIG. 2D. After singulation, the conventional chip package 100 is obtained as presented in FIG. 1B.
FIG. 3 depicts a side view of the chip package in FIG. 1B while connected to the printed circuit board (PCB) 140. In FIG. 3, the chip package 100 is fixed to the PCB 140 by connecting the solder balls 109 to the bonding pads 142, resulting in the chip package 100 electrically connected to the PCB 140. The plastic mold 116, the wires 112 and 114 are seated on the topside 118 of the substrate 102 while the bottom side 132 of the die 104 is exposed to the atmosphere. However, the bottom side 132 of the die 104 is not connected with the surface 145 of the ground layer 144 by soldering so that heat generated by the die, which must typically be drawn from the chip through package interconnects, can not be efficiently dissipated to the outside or the atmosphere by the ground layer 144 of PCB 140.
Moreover, the plastic mold 116 and the wires 112, 114 are seated on the topside 118 of the substrate 102, and the solder balls 109 are seated on the bottom side 110 of the substrate 102; therefore, the overall thickness H4 of the conventional chip package 100 is larger than 0.5 mm. This obstacle cannot be surmounted by applying conventional process of making the chip package. In addition, procedures of taping and de-taping not only make the process more complicated but also increase the cost.
It is therefore an object of the invention to provide a super low profile package with high efficiency of heat dissipation. The chip package possesses the small size and high efficiency of heat dissipation. Besides, the elimination of conventional procedures of taping and de-taping decrease the production cost.
The invention achieves the above-identified objects by providing a super low profile package with high efficiency of heat dissipation. The chip package includes the substrate, the heat sink, the die, the wires and the plastic mold. The substrate has a cavity. A number of the solder balls and a ground ring are seated in the bottom side of the substrate, and the extending part of the heat sink adheres to the ground ring. The die is seated in the cavity, wherein the die has a first die surface adheres to the heat sink. In addition, the die is electrically connected to the. substrate by the wires, wherein the wires are bonded on the first die surface and the first substrate surface. The plastic mold encapsulates the die, the heat sink and the wires.
The invention achieves the above-identified objects by providing a process of making a super low profile package with high efficiency of heat dissipation. First, a substrate is provided while a ground ring is seated in the bottom side of the substrate, and a cavity is formed in the substrate. Second, the extending part of the heat sink adheres to the ground ring. Third, the die is seated in the cavity, and the front die surface adheres to the heat sink while parts of the front side of the die for bonding the wires are exposed. Fourth, wire bonding proceeds; two ends of the wire are separately bonded on the die and the substrate. Then, encapsulation is proceeds, wherein the bottom side of the die is filled with the plastic mold. The plastic mold encapsulates the die, the heat sink and the wires. Next, the solder balls are adhered on the bottom side of the substrate. Finally, singulation proceeds.